Forum Discussion
ContributorQuartus Support for Post Route Simulations
If you mean a post-fit timing analysis, then yes, but I presume you are referring to a true gate-level simulation. This was possible in the past, but newer larger devices have made it such that it's usually impractical to do this (hours or days to run the sim), so gate-level simulation models are not provided. The combination of a functional simulation and timing analysis is usually considered sufficient for verification.
Super ContributorAdditionally, timing simulation is not supported for Arria V, Cyclone V, Stratix V, and newer families. If your device does not support timing simulation, use the Timing Analyzer rather than gate-level timing simulation.
Gate-level timing simulation is supported only for the Arria II GX/GZ, Cyclone IV, MAX II, MAX V, and Stratix IV device families.
Reference: https://www.intel.com/content/www/us/en/docs/programmable/683080/22-1/simulation-levels.html
Best Regards,
Richard Tan
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