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Oliver_I_Sedlacek's avatar
Oliver_I_Sedlacek
Icon for Contributor rankContributor
2 years ago
Solved

Quartus Pro an Lite different handling of VHDL entities problem

I've been developing a design in VHDL under Quartus 20.1 Lite and the time has come to migrate it to Quartus 23.1 Prime Pro. It's giving me a real headache because Pro is choking on stuff that compil...
Programmable Logic Device
  • ShengN_altera's avatar
    ShengN_altera
    2 years ago

    Hi,


    Have to use something like below:

    rsm: entity work.spi_master_writeonly generic map (.....) port map(....)


    Also can do like below as well:

    use work.spi_master_writeonly;

    ...

    rsm: spi_master_writeonly generic map (.....) port map(....)


    Pro version is more strict compared to Lite version.


    Thanks,

    Best Regards,

    Sheng


    p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer.


ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,


Have to use something like below:

rsm: entity work.spi_master_writeonly generic map (.....) port map(....)


Also can do like below as well:

use work.spi_master_writeonly;

...

rsm: spi_master_writeonly generic map (.....) port map(....)


Pro version is more strict compared to Lite version.


Thanks,

Best Regards,

Sheng


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer.


Oliver_I_Sedlacek's avatar
Oliver_I_Sedlacek
Icon for Contributor rankContributor
2 years ago

Thanks for that. I don't suppose there's a document that lists these differences in strictness, as I'm seeing other problems?

Not being a VHDL guru I'm surprised that these differences are allowed in the language specification.