Forum Discussion
Altera_Forum
Honored Contributor
10 years agoI figured it out.
The design was originally meant to target a Virtex 7. I was trying to port to a Cyclone V. Quartus had an issue attempting to use Xilinx IP and trying to initialize large BRAMs. Basically large portions of the code need a re-do. It would be nice to have had a better error description though.