Quartus Logic Lock flow

There's no user guide dedicated exclusively to Logic Lock. It's a feature that is part of other design flows so it is described in the user guides where needed. Floorplanning a design well is something of an art and learned from experience. But to get started, it depends on what you're trying to. If you are indeed going to be using partial reconfiguration (or any block-based flow), I'd recommend starting by compiling the full design (for PR, this is the base compile) with no Logic Lock regions set. Then, using cross-probing and the reporting features in the Chip Planner, see where the logic you need to isolate gets placed by the Fitter. Create an LL region for the PR region logic (and for PR, a related routing region) in about the same area, making it a bit larger than what you might think you need to allow for the boundary LUTs required for PR and for room to grow in the future. Recompile and see how you did, making sure to perform a timing analysis to make sure your design still meets performance requirements (very very important for the PR flow).

This flow for the use of LL regions is also good if you just want to use incremental block-based compilation or design block reuse. See what the Fitter chooses on its own first and then create a floorplan similar to what you get from the tool.

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