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Am I missing something? The IP Catalog for generating verilog does not provide a waitrequest signal??
in real life, on-chip mem will assert backpressure with a waitrequest. However, the IP at IP Catalog>On Chip Memory> 2-Port RAM does not allow configuration for one or generate the signals and logic. Am I missing something? I assume I'll have to build it in....I realize this small thing was what was throwing off my synthesized application.
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Since when? On chip FPGA memory is implemented as SRAM blocks, so it is purely a slave that responds after a fixed delay. There is typically no
waitrequest handshake provided.
waitrequest I believe is specific to the Avalon bus interface spec, so you would need to find an IP block that is implemented for the Avalon bus.
Can you give an example of ON CHIP FPGA memory that has such a feature? I could see that an SDRAM controller (which has embedded refresh controller) and has a variable response delay could provide such a response handshake, but this would be controlling external SDRAM devices.
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