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AVale22's avatar
AVale22
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6 years ago
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Quartus II: Help with bus out and bus in ports

Hi, sorry for stupid question ๐Ÿ˜† , newbie with bus, as you can see I have done 3 chips in vhdl, one without vector, that is simple but bad vhdl code (not optimal) the I have done the other 2 with vector question is how do connect a out bus to a different in port bus, and also the one I have reuse how do i connect different signal to same but different bus ???

see attach image, thx in advance for help ๐Ÿ˜ƒ

Of course I will want use vectors in VHDL so first chip will be change to vector if bus issues solved ๐Ÿ˜€

  • Hi,

    Please check the below solution & take care the rest of the connection in your project like cc[cc[3..1],cc[0]], ccc[ccc[3..1],ccc[0]] & y[y[7..2],y[1],y[0]] etc.

    Please let me know if you have any different concern.

    If possible you can share the project file *qar file('Project' Menu -> 'Archive Project').

    Regards,

    Vicky

2 Replies

  • Vicky1's avatar
    Vicky1
    Icon for Regular Contributor rankRegular Contributor

    Hi,

    Please check the below solution & take care the rest of the connection in your project like cc[cc[3..1],cc[0]], ccc[ccc[3..1],ccc[0]] & y[y[7..2],y[1],y[0]] etc.

    Please let me know if you have any different concern.

    If possible you can share the project file *qar file('Project' Menu -> 'Archive Project').

    Regards,

    Vicky

  • AVale22's avatar
    AVale22
    Icon for New Contributor rankNew Contributor

    Thx, that was what I was think was to solved it :), have apply that and it work fine :)