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AGofs's avatar
AGofs
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Quartus II 18.1 lite edition in system memory editor

Good afternoon , I'm working with 18.1 lite edition with my new FPGA design. I can program FPGA successfully, and then I'm opening InSystem Memory Editor . JTAG ready and USB-Blaster found. I ...
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ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,


Have you properly timing constraint the jtag? Template can be found by go to Insert Template -> Timing Analyzer -> SDC Cookbook -> Jtag Signal Constraints.

Or may be try to lower the programming frequency.


Thanks,

Best Regards,

Sheng


AGofs's avatar
AGofs
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hi Sheng,

I will check this issue, but I always used default constraints- and it works.