Forum Discussion
SXian3
New Contributor
New ContributorQuartus failed to compile Verilog code generated by AOC compiler
Environment: Intel vLab servers quipped with Stratix-10 PAC. Software: Quartus Pro 18.1.2 with patches + acceleration stack d5005_ias_2_0_pv I was trying to compile a simple OpenCL program into ver...
JohnT_Altera
Regular Contributor
Regular ContributorHi,
If you would like to genrerate C to RTL then I would recommend you to use HLS flow. Please refer to https://www.intel.com/content/www/us/en/programmable/documentation/div1537518568620.html.
The reason is that I do not think the Arria 10 PAC is able to support OpenCL to generate RTL only.
