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SXian3's avatar
SXian3
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5 years ago

Quartus failed to compile Verilog code generated by AOC compiler

Environment: Intel vLab servers quipped with Stratix-10 PAC. Software: Quartus Pro 18.1.2 with patches + acceleration stack d5005_ias_2_0_pv I was trying to compile a simple OpenCL program into ver...
JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

When you mention the same error on private server, may I know the step you used and could you share with me your project so that I can duplicate the issue?

  • SXian3's avatar
    SXian3
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    5 years ago

    I tried Quartus 17.4 and 19.1, but neither of them actually worked. In Quartus 19.1, I sourced the setup scripts to make the ENV variables are set correctly (e.g. INTELFPGAOCLSDKROOT e.t.c), and then I ran `aoc -rtl gems.cl` to generate RTL and change to the work directory. There is a XML file named `board_spec.xml` in the folder, and I just followed the commands in that XML to run the compilation.

    For Quartus 17.4, it is almost the same steps, except that I have to use `aoc -c gemm.cl` to generate the RTL. I can share you with source code I have to reproduce the issue (you need to replace the TXT extension with CL). Thanks!