Forum Discussion
SXian3
New Contributor
6 years agoQuartus failed to compile Verilog code generated by AOC compiler
Environment: Intel vLab servers quipped with Stratix-10 PAC. Software: Quartus Pro 18.1.2 with patches + acceleration stack d5005_ias_2_0_pv I was trying to compile a simple OpenCL program into ver...
JohnT_Altera
Regular Contributor
6 years agoHi,
I suspect that this might be related to the Vlab setup issue. Please create new forum case in https://communities.intel.com/groups/harp so that they can help related to Vlab related issue.
- SXian36 years ago
New Contributor
Okay. Thanks John.
Actually I tried the same command on a private server, and got some similar errors... Have no idea what's going wrong.