Quartus Error 35030

I have a Cyclone V HPS design on the SoCKit board which includes some custom logic connecting to LOANIO.

My custom logic basically replaces the SPIM0 module in the HPS, so I took the SPIM0[CLK, MISO, MOSI, SS] and clicked LOANIO so I could pass them to the outside world.

I initially got the 12016 error "Net hps_spisensor_MISO", which fans out to '<long text...>LOANIO69' is connecting a Partition with logic other than a single Bidirectional pin". I wasn't sure what this meant, but I got rid of the error by changing my ghrd_top.v file's, MISO declaration from "input" to "inout". This seemed fishy. The below errors are all for the remainder of the signals in my custom logic, which are all outputs.

Next I started seeing error 35030: "Partition "<long text>:border" contains I/O cells that do not connect to top-level pins or have illegal connectivity"

Followed by several 35032: "Output port '<long text>hps_io_gpio_inst_LOANIO57[0]' on partition '<long text>:border' must drive a top level pin but is driving '<long text> :border|gpio_inst".

Followed by several 13176: "Port I_GPIO1_PORTA_I of HPS atom '<long text>hps_gio_gpio_inst_LOANIO57[0]~output' must be connected to a top level pin"

etc, etc.

Below shows the relevant portions of the "ghrd_top.v" file showing how I'm doing the loan IO.

`include "top/config_soc.v"

module ghrd_top (

output wire hps_spisensor_CLK,

output wire hps_spisensor_MOSI,

inout wire hps_spisensor_MISO, // I had to change this from input to inout

output wire hps_spisensor_CSN,

);

// internal wires and registers declaration

wire [66:0] loan_io_in;

wire [66:0] loan_io_out;

wire [66:0] loan_io_oe;

wire spisensor_clk_internal;

wire spisensor_mosi_internal;

wire spisensor_miso_internal;

wire spisensor_csn_internal;

assign loan_io_out[57] = spisensor_clk_internal;

assign loan_io_out[58] = spisensor_mosi_internal;

assign loan_io_out[59] = 1'b0; // arbitrary

assign loan_io_out[60] = spisensor_csn_internal;

assign loan_io_oe[57] = 1'b0;

assign loan_io_oe[58] = 1'b0;

assign loan_io_oe[60] = 1'b0;

assign spisensor_miso_internal = loan_io_in[59];

soc_system u0 (

.hps_0_h2f_loan_io_in (loan_io_in),

.hps_0_h2f_loan_io_out (loan_io_out),

.hps_0_h2f_loan_io_oe (loan_io_oe),

.hps_0_hps_io_hps_io_gpio_inst_LOANIO57 (hps_spisensor_CLK),

.hps_0_hps_io_hps_io_gpio_inst_LOANIO58 (hps_spisensor_MOSI),

.hps_0_hps_io_hps_io_gpio_inst_LOANIO59 (hps_spisensor_MISO),

.hps_0_hps_io_hps_io_gpio_inst_LOANIO60 (hps_spisensor_CSN),

.sensormaster_0_sensorconduit_spi_clk_out (spisensor_clk_internal),

.sensormaster_0_sensorconduit_spi_cs_n (spisensor_csn_internal),

.sensormaster_0_sensorconduit_spi_miso (spisensor_miso_internal),

.sensormaster_0_sensorconduit_spi_mosi (spisensor_mosi_internal),

);

endmodule

I could not paste the image properly, so attached are some snapshots.

https://alteraforum.com/forum/attachment.php?attachmentid=14044&stc=1

https://alteraforum.com/forum/attachment.php?attachmentid=14044&stc=1