Quartus complain about LVDS pin assignment for MAX V CPLD device

Thats the worng way of going about LVDS. To work with LVDS signals, you need not generate both _n and _p signals in your VHDL code. The logic will be single-ended only, ie , you will have only the OUT signal as single-ended from your logic.

To get LVDS signals, you just assign the OUT signal to an LVDS IO pin and change the IO Standard to LVDS. The Pin planner will automatically assign the OUT_n pin to the next adjacent LVDS pair for that pin.