Quartus 18.1 - CYCLONE V Preloader issue

Hi

Am working on a project with CYCLONE V - 5CSXFC6D6F31C8N with Quartus 18.1. After compilation in emif.xml file in the hand off folder the SDRAM related clock info is being written as 0 by quartus. The preloader doesn't work therefore.

We had to manually set the value to make it work. But not sure this is the best value. Please suggest appropriate values for these.

Our EOSC input for HPS is 25MHz. We are not using f2h_sdram_ref_clk. Memory clock frequency is 300 MHz.

Best Regards

Syam