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Altera_Forum's avatar
Altera_Forum
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8 years ago

Quartus 17 position of symbol labels different for VHDL and block diagram/schematic

When I create a symbol from a VHDL file, the labels are lined up with the pins properly. (center aligned) But when I create a symbol from a block diagram/schematic file, the labels are below the p...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi,

Yes,It may be bottom alignment by default in case of "symbol from a block diagram/schematic file".

Can be changed/edit it manually(By using edit selected symbol option).

Let me know if you need any further assistance.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)