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Altera_Forum
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9 years ago

Quartus 15.1 issue for altsyncram

Hi,

I am using Quartus 15.1 prime , in that When I instantiate a altsyncram it errors out for Arria 10 Gx ,the error message is as follows:

Info (12128): Elaborating entity "rr4096x8_32r_2p" for hierarchy "sdh:Csdh|stm4in:Cstm4in|wrctrl:Cwrctrl|rr4096x8_32r_2p_shell:\g1:0:Crr4096x8_32r_2p|rr4096x8_32r_2p:Crr4096x8_32r_2p"

Info (12128): Elaborating entity "rr4096x8_32r_2p_altsyncram_5n21" for hierarchy "sdh:Csdh|stm4in:Cstm4in|wrctrl:Cwrctrl|rr4096x8_32r_2p_shell:\g1:0:Crr4096x8_32r_2p|rr4096x8_32r_2p:Crr4096x8_32r_2p|rr4096x8_32r_2p_altsyncram_5n21:rr4096x8_32r_2p_altsyncram_5n21_component"

Error (12024): WYSIWYG primitive "ram_block1a_0" is not compatible with the current device family

Error (12024): WYSIWYG primitive "ram_block1a_1" is not compatible with the current device family

Error (12024): WYSIWYG primitive "ram_block1a_2" is not compatible with the current device family

Error (12024): WYSIWYG primitive "ram_block1a_3" is not compatible with the current device family

Error (12024): WYSIWYG primitive "ram_block1a_4" is not compatible with the current device family

Error (12024): WYSIWYG primitive "ram_block1a_5" is not compatible with the current device family

Error (12024): WYSIWYG primitive "ram_block1a_6" is not compatible with the current device family

Error (12024): WYSIWYG primitive "ram_block1a_7" is not compatible with the current device family

the design was earlier compiled in cyclone v .

the intended file even won't open using megawizard function, although it is qsys in quartus 15.1 via ip catalogue.

waiting for quick reply.......

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    It's exactly what it says. You can't use that type of ram block in the Arria 10. FPGA development is not like software where you can just bring in any code that will fit. Your FPGA consists of various types of hardware. Other types of FPGA consist of different hardware. They both may be ram blocks but that doesn't mean they can be used in a given FPGA. You can infer memory by carefully writing your HDL code so that Quartus will use the available memory resources. Another way to get a memory block is to use the IP catalog to create a module containing the memory you need.