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Altera_Forum
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14 years ago

Qsys SDRAM wire export, clk missing

Hi All, This is a newbie question. I don’t have much luck adding SDRAM to my project. I’ve completed the “Nios II Hardware Development Tutorial” and the first count binary demo is worki...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Ok, I got it. At first it's not an error of Qsys not wiring out the SDRAM Clock.

The User has to export an own clock signal in Qsys, i.e. from the PLL, for the SDRAM Clock. Doing this you will recognize the signal/wire in Quartus Pin Planner and you can root it to the specific FPGA Pin.

My whole system works fine now.