Honored Contributor
Honored Contributor[edit]
Actually you can ignore my post below. DRAM_ADDR[12] in connected to NC on the schematics so it is not used. Anyone could share a simple SDRAM template for qsys? Thanks for responding. Not connecting the clock was definitely a problem. I was studying the sample projects provided by Terasic (DE0 board) . I’ve modified the core from Nios/f to Nios/e in the SOPC sample project and I was able read and write to SDRAM. This is great but Terasic only provides SOPC and not Qsys examples. I’d like to build my project from scratch with Qsys. The two is quite different and I cannot figure out what I’m doing wrong with Qsys. I’ve copied the timing values from SOPC but there seems to be a problem with the Data and Address PIN assignments. DRAM_ADDR[12] the last PIN in the Terasic example is not showing up in Qsys. I’ve attached Qsys wire exports to my previous post. SPOC Sample Project: (where all pins are correct) /////////////////////// SDRAM Interface //////////////////////// inout [15:0] DRAM_DQ; // SDRAM Data bus 16 Bits output [12:0] DRAM_ADDR; // SDRAM Address bus 13 Bits output DRAM_LDQM; // SDRAM Low-byte Data Mask output DRAM_UDQM; // SDRAM High-byte Data Mask output DRAM_WE_N; // SDRAM Write Enable output DRAM_CAS_N; // SDRAM Column Address Strobe output DRAM_RAS_N; // SDRAM Row Address Strobe output DRAM_CS_N; // SDRAM Chip Select output DRAM_BA_0; // SDRAM Bank Address 0 output DRAM_BA_1; // SDRAM Bank Address 1 output DRAM_CLK; // SDRAM Clock output DRAM_CKE; // SDRAM Clock Enable Is there any way to change the wire assignment in Qsys? Of course I could just use SPOC and forget about Qsys… Thanks, James
