Qsys generates. but analysis/synthesis error

Hi,

I'm facing this weird error and can't seem to get my design to compile.

The work around suggested is weird. I tried increasing the ram size and adding a dummy address range extender component.

But it still doesn't work properly.

I've tried removing components from my design and deleting the db directory as well. But it still gives an error.

Has anybody faced/solved this?

Thanks

Zubair

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