Open Side Menu
Skip to contentBrand Logo
Forums
BlogKnowledge BaseAltera.com
RegisterSign In
  1. Altera Community
  2. Forums
  3. FPGA Device

Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

QII configures D3 & D1 delay chains incorrectly for ALTDDIO in IOE - Tsu/Th err

I posted this for better description of the problem. Please see below post for detailed technical description.

http://www.alteraforum.com/forum/showthread.php?t=48866 (http://www.alteraforum.com/forum/showthread.php?t=48866)
No RepliesBe the first to reply

Recent Discussions

  • FabianL's avatar
    Arria 10: Remote Update Factory Fallback won't work & Watchdog does not trigger
    2 hours ago
    FabianL
  • jaykrishna1's avatar
    Vcm for the clock input pins of agilex5 E-series FPGA A5ED065BB32AE5SR0
    2 hours ago
    jaykrishna1
  • kraichle's avatar
    Can you Validate MAX10 Date and Lot Code?
    2 hours ago
    kraichle
  • Santoshmbca's avatar
    Part Status request
    2 hours ago
    Santoshmbca
  • Vigneswaran's avatar
    Agilex 7 Decoupling capacitor scaling factor
    2 hours ago
    Vigneswaran
Contact Us
Altera YoutubeAltera YoutubeAltera Twitter
  • Company Overview
  • Newsroom
  • Our Leaders
  • Careers
Subscribe to Altera Newsletter

© Altera Corporation | Terms of Use | Privacy Policy | Cookies | Trademarks | PSIRT

Altera Logo