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The pulse can be generated using counters, or a reloadable counter with selectable input count. The counter could be controlled by a small finite state machine. I've built designs like this for generating pulses relative to a 1pps (pulse-per-second) GPS pulses.
I would assume the DE-nano have 3.3V output pins, so that will satisfy your pulse voltage amplitude requirement.
Is the pulse generator just supposed to start and run whenever the FPGA is loaded, or will it be externally triggered? Will it need control registers, eg., to enable output pulse generation? How accurate does the timing of this pulse need to be, i.e., is the oscillator on the board accurate enough, and could you tolerate jitter on the pulse edges?
You could implement the design purely in FPGA logic using an HDL, or you could implement the pulse using a processor to toggle an I/O pin (which could potentially led to edge jitter), or you could use a pulse-generator component that is controlled by a processor, eg., a PWM generator peripheral.
Cheers,
Dave
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thanks, Dave. the generator could start when fpga is loaded. and i just use this pulse to roughly trigger other device. so the accuracy and the jitter won't be a problem for me. so i just need a straightforward way to generate the pulse from the board.
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