proporgation delays

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Hello Folks,

Ref: Aletra Quartus 2 Web Edition.

I have a question regarding propagation delays, I am trying to show how propagation delays add when gates are cascaded (simple AND for example). I am using the and2 gates and performing Timing analysis, this shows a delay for one gate only it does not add the delays as the input passes from input to output. Is there any way to get around this? I have also tried to use classic timing and add points of delay however after the first gate the delay time is N/A.

I hope I have explained my self clearly. To give my question some context, I am trying to construct from basic gates A 4-bit ripple full adder and a 4-Bit Carry look ahead adder and show the benefits of using the latter as it’s quicker. However because I can not get more then 1 propagation delay am stuck. Would appreciate your help.

Jag.

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Hi,

what you are trying is difficult to achieve with FPGA's. First you have to keep in mind that logic will be implemented in the lookup tables in the Logic Cells of the FPGA's. Depending on the used FPGA type the LUT could have up to 7 inputs and one output. That means more than one and2 will be implemented. You can force Quartus to put every and2 in a seperate LCELL by using the attribute "implement as LCELL output". Have a look in the Quartsu help. Second problem is that in the newer FGPA's the propagating delay is dominated by the routing delay. You could not expect that the dealy will increase by a fix number.

It is not require to write an adder implementation with gates. The synthesis engine will recognize addition in your source code and will implement the adder by using the build-in

adder structures ( at least true for newer devices).

Kind regards

GPK