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Altera_Forum
Honored Contributor
11 years agoI have a similar setup, but I am just trying to use the NIOS to program the PROM for future RTL updates so my application is very small and fits in block RAM so no separate application image is needed. Here is what I learned:
- The JIC must be set to Active Serial X1 mode. If set to X4 mode any future FPGA images converted with sof2flash will not work. The JIC will set the addressing mode and the dummy clocks which varies between X1 and X4 and breaks configuration if not set correctly.
- If you are using a Stratix V AB device, or possibly any V series, and the Altera flash software library you must go into the code and disable the reverting to 3-byte addressing mode. I found this in the epcs_commands.c file, which appears to have been written before V series devices came out and never updated. If you don't do this you need to power cycle the system to reset the PROM's addressing mode to whatever the JIC configured.