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You do have the 'real' licence for a nios /f core?
Otherwise the cpu will only run while the jtag is connected.
It might also be possible to debug the epcs bootloader using the jtag debug.
If nothing else it ought to be possible to use signaltap - especially if you expose the nios 'soft reset' line.
For software updates it ought to be possible to just rewrite the epcs sectors that contain the code (from code running on the nios)
However the HAL functions for this are a little horrid.
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I'm using the /e version, which does not require a license for this (that is according to our FAE). I've been able to now program the flash device with the flash I created from the elf2flash utility after the FPGA has been configured. However, the processor stays paused. I'm thinking this may be related to stdin/stdout (I had been using JTAG UART), and this could possibly cause problems with the processor resetting.
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