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Altera_Forum
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14 years ago

Programming Harware

I'm an Altera newbie and am designing a board for a Cyclone III EP3C5E144I7N FPGA. I purchased a USB Blaster cable for configuration/programming. What typical hardware would need to be on the board to interface with the 10 pin USB Blaster connector? Would the JTAG TCK, TDO, TMS, and TDI signals go directly from the connector to the FPGA? What else is needed to program an onboard flash device and to configure the FPGA from it during power up?

Any documentation and/or design examples you could recommend would be appreciated. Thanks.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    For the a minimum partcount configuration scheme with serial flash configuration memory and JTAG connector, you can refer to figure 9–30. programming serial configuration devices in-system using the jtag interface in the Cyclone III device manual. It uses indirect JTAG programming of the flash memory.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thanks for the responses.

    I plan on using the circuit shown in figure 9–30, programming serial configuration devices in-system using the jtag interface in the Cyclone III device manual. What should the MSEL pins be connected to using this circuit? Once the serial configuration device has been programmed in system through the FPGA, does the circuit then operate in an active serial configuration manner on subsequent power ups as the serial configuration device configures the FPGA? If so, Table 9-7 indicates a MSEL2=0, MSEL1=MSEL0=1 for my desired 2.5V supply and standard POR time.

    Aside from the circuitry differences, what operational differences exist between programming with the circuits shown in Figure 9-30 (Programming Serial Configuration Devices In-System Using the JTAG Interface) and Figure 9-7 (In-System Programming of Serial Configuration Devices?) What are the pros and cons of each and what would you recommend?