Programming Error

Can anyone help me fix this error? :rolleyes:

`timescale 1 ps / 1 ps
module top (reset, clk);
 input   clk;
 input   reset;
 bit  counter;
 always @ (posedge clk or posedge reset)
 begin
   counter ++;
  if (counter > 1000)        // Error here
   begin
    counter = 0;
   end
 end
endmodule

Error (10200): Verilog HDL Conditional Statement error at top.sv(35): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct