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Altera_Forum's avatar
Altera_Forum
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14 years ago

Programming Error

Can anyone help me fix this error? :rolleyes: 

`timescale 1 ps / 1 ps
module top (reset, clk);
 input   clk;
 input   reset;
 bit  counter;
 always @ (posedge clk or posedge reset)
 begin
   counter ++;
  if (counter > 1000)        // Error here
   begin
    counter = 0;
   end
 end
endmodule


Error (10200): Verilog HDL Conditional Statement error at top.sv(35): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    there it is.

    since this is not C/C++, you can not use "count++"

    --- Quote Start ---

    `timescale 1 ps / 1 ps

    module top (reset, clk);

    parameter MAX_COUNT = 1000;

    input clk;

    input reset;

    reg [31:0] counter;

    always @ (posedge clk or posedge reset)

    if( reset )

    begin

    counter <= 0;

    end

    else

    begin

    counter <= counter + 1;

    if (counter >= ( MAX_COUNT - 1) ) // Error here

    begin

    counter = 0;

    end

    end

    endmodule

    --- Quote End ---