Programming CPLD second time

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This would indicate to me that the CPLD has an issue with too much power

draw on the second programming attempt since the device is drawing power due to toggling flops and such or ?

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That sounds like a pretty random guess to me :)

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My idea was to use the DEV_OE pin to keep the CPLD quiet during programming, or are there other tricks here we can use ?

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You need to attack the problem systematically.

Lets start with your above hypothesis. Too much power. Ok, create a configuration that requires almost no power, eg., it blinks an LED. Download that configuration. Does the second configuration fail?

Its more likely that you have either; a power issue (voltage regulation), a clock issue, or JTAG signal integrity issues.

What CPLD are you using?

Cheers,

Dave

DEV_OE functionaility has to be enabled in the CPLD code, you should know if it has any effect in your case. Stopping the input clock would be the most promising method to suppress possible interferences,

I generally agree about the random guess. By the way, an effective method to lock up further JTAG programming would be to disable the JTAG interface in the design.