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MDuse's avatar
MDuse
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7 years ago

Program not working as expected

Hi, my device consists of MCU, MAX V CPLD and sensor device. MAX V CPLD is used to interface sensor to MCU. I have a code in VHDL for MAX V CPLD: entity Device is port ( clk16: in std_logic...
  • MDuse's avatar
    MDuse
    Icon for New Contributor rankNew Contributor
    7 years ago

    But it is bidir which should be good for me as long as CPLD can set bidir pin to 0 and to high impedance state and is able to read its state.

    So, can you confirm, that this implementation that is present in my code:

    if start = '0' then
   start <= '0'; 
end if;

    is bad idea and I should do it in some official way?