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MDuse's avatar
MDuse
Icon for New Contributor rankNew Contributor
7 years ago

Program not working as expected

Hi, my device consists of MCU, MAX V CPLD and sensor device. MAX V CPLD is used to interface sensor to MCU. I have a code in VHDL for MAX V CPLD: entity Device is port ( clk16: in std_logic...
JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
7 years ago
Hi, The Max V IO pins support open drain but it will depending on you implement it. You should be able to look into your Quartus fitter result to see if the pin is configured as open drained. Have you tried to performed simulation to see if you are implementing it correct?
MDuse's avatar
MDuse
Icon for New Contributor rankNew Contributor
7 years ago

This is pinout for start signal (output of Fitter):

Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment

start: 44 : bidir : 3.3-V LVTTL : : 2 : Y

I simulated it and was not able to reproduce the issue. I tried to move falling edge of start signal relative to clk_out clock to several positions when simulating, but the issue never happened when simulating.