Forum Discussion
MDuse
New Contributor
7 years agoProgram not working as expected
Hi, my device consists of MCU, MAX V CPLD and sensor device. MAX V CPLD is used to interface sensor to MCU. I have a code in VHDL for MAX V CPLD: entity Device is
port (
clk16: in std_logic...
sstrell
Super Contributor
7 years agoYou're doing a check for rising_edge(clk_out) inside a process that is only sensitive to clk16. Your next state logic should be in a separate process, sensitive to clk_out.
Also, you need to code your bidirectional (or is it supposed to be a tri-state?) correctly. It should look something like this (replace from_core and to_core with what the pin should be when it's an output and when it's an input:
start <= from_core WHEN oe='1'
ELSE 'Z';
to_core <= start;There should be some type of output enable control signal for an inout.
Finally, you're doing an if check on start being 0, but then setting start to 0 as an action in that same if check. I'm not sure what you're trying to do.
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