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SDavi9's avatar
SDavi9
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Processor interface to transceiver PHY

I have been looking into the design process for implementing a (Optical) transceiver interface in within a Intel FPGAs. How / where does the processor (e.g. Nios) that is to be responsible for the tr...
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aikeu's avatar
aikeu
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi SDavi9,

I have consulted the team and there are only some reference available for fmc loopback as below but not specific to your request:

https://www.intel.com/content/dam/support/us/en/programmable/support-resources/fpga-wiki/asset03/cyclone-10-gx-xcvr-toolkit-reference-design-user-guide.pdf

https://www.eeweb.com/wp-content/uploads/articles-app-notes-files-implementing-intel-cyclone-10-gx-triple-rate-sdi-ii-with-nextera-fmc-daughter-card.pdf

Thanks.

Regards,

Aik Eu

SDavi9's avatar
SDavi9
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Dear Aik Eu,

Thank you for your response !

The first reference I have already seen - however this seems to be only a loop back and doesn't give me any details how I would connect and use a NIOS processor with it ? I need to know how to transfer data from the NIOS out of the FPGA via the optical interface ???

The 2nd design also appears to be a loop back design and I don't see where the NIOS would be connected. Also it appears to be a SDI design and not a Optical interface ?

Best regards

Shmuel