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Altera_Forum's avatar
Altera_Forum
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17 years ago

Problems writing/reading to SSRAM with Cyclone III starter board

Hello, I have been learning to work with the Cyclone III starter board with the goal of creating a device for an undergraduate project. I have no previous experience in digital design, and onl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

A few things I'd check. Check the SSRAM clock. It has to be 180 degrees out of phase than your data so that it can capture into the RAM.

For the buffer questions, my design for Cyclone II board (not Cyclone III), I use the LVTTL 3.3V. Data has to be bidirectional, the rest (adsc,bw,bwe,chipenable, outputenable and address) will be single direction from the FPGA to the SSRAM.