Problems HD44780 - LCD - ALTERA DE2-115...

Obviously I'm reviving an old thread here.... so perhaps this will help out future readers.

Regarding the code posted:

I noticed that your Clock process.......... as shown below:

process(clk)
begin
if trigger2='1' then -- a switch to turn the lcd on and off
lcd_an<='1';
lcd_rw<='0'; -- setting the rw permenantly to 1
else
lcd_an<='0';
end if;

You have the port "clk" declared within your entity:

clk : in std_logic;

However I don't see any process that uses the "clk" port at all.... anywhere within your code.

A clock is needed for the FPGA to create the required timing signals.

Usually you have a clock process similar to what is shown below, in order to generate the specific timing signals you need for the display you are using.

The Altera DE2 uses the standard HD44780 LCD display, and it requires a 400Hz clock signal.

Using the 50Mhz clock source on the DE2, Your process would look something like this:

--======================= CLOCK SIGNALS ============================--  
process(clock_50)
begin
      if (rising_edge(clock_50)) then
         if (reset = '0') then
            clk_count_400hz <= x"00000";
            clk_400hz_enable <= '0';
         else
            if (clk_count_400hz <= x"0F424") then           
                   clk_count_400hz <= clk_count_400hz + 1;
                   clk_400hz_enable <= '0';
            else
                   clk_count_400hz <= x"00000";
                   clk_400hz_enable <= '1';
            end if;
         end if;
      end if;
end process;  
--==================================================================--

The statement in the above code:

"IF (clk_count_400hz <= x"0F424") THEN"

This is just the HEX reset value for the counter that is needed when using a 50Mhz source. This creates your 400Hz signal that is needed.

The Process for your State machine should begins with an IF THEN ELSIF statement to provide the appropriate 400Hz clocking

to drive the State machine through its various states.

Place the following code before your State machines "CASE state IS" statement.

As shown below:

process (clock_50, reset)
begin
        if reset = '0' then
           state <= reset1;
           data_bus_value <= x"38"; -- RESET
           next_command <= reset2;
           lcd_e <= '1';
           lcd_rs <= '0';
           lcd_rw_int <= '0';  
    
    
    
        elsif rising_edge(clock_50) then
             if clk_400hz_enable = '1' then  
                 
             
                 case state is
                        |
                        |
                        \/
               Proceed with your State machine Statements...........

Now for those of you that are interested......

I have recently made a detailed instructional video on how to drive the HD44780 using VHDL.

I also Demo the code on an Altera DE2 board. So feel free to review this if need be.

https://youtu.be/ciimbdyj7w4 (https://youtu.be/ciimbdyj7w4)

Cheers!

-Gerry

http://www.digital-circuitry.com (http://www.digital-circuitry.com)