Problems about the DCFIFO megafunctions

Hi,

Functional simulation checks the logic functionality ignoring clock speed/delay issues. It must pass before any timing model passes.

timing model checks if it then passes given speed/device.

fast model assumes best speed device to tell you if your timing can pass best case in case you are not sure about a failed case. Once it passes then you know it does in best case.

for dc fifo words there are two clock domains. if you want to read the value then read it on the relevant clock because there is latency between them and the values will not be same at a given point in time. Moreover you should not read a value generated by one clock on the other's clock as timing violation occurs in the read logic.