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Altera_Forum's avatar
Altera_Forum
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18 years ago

Problems about DDR2!

Error: Too many output and bidirectional pins in I/O bank 3 assigned near VREF pin AB11 (VREFGROUP_B3_N1) on device EP3C120F780C7 -- no more than 9 output and bidirectional pins allowed near the VREF...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

VCCIO/GND pairs are distributed accross the chip to minimize the I/O switching noise. There is no hard delimited VCCIO groups within an I/O bank.

There is no information (as far as I know) about which I/O pins are close to each VCCIO pair. The closest information we have is the VRef groups, that's why I suggested you use that as a guideline for placing your I/Os.

Just try to keep 9 or less outputs/bidirs in each VRef group. You can try having more, but you will have to run the fitter repeatedly to see if Quartus accepts it. As a rule, make sure you lay out the schematic/PCB AFTER you have successfully placed your pins and ran the fitter with no errors.