problem with verilog simulation in modelsim altera

For adding libraries, I always use the following as a template:

http://www.altera.com/support/examples/tcl/tcl-modelsim.html?gsa_pos=1&wt.oss_r=1&wt.oss=tcl%20modelsim

It's a little outdated, I think, and by default loads in way too much, but really gets you started.

When adding the .sdf files, did you apply/bind them to the proper hierarchy? I haven't done timing sims in a while, but thought this had to be done(i.e. you didn't just add them and let the tool figure it out.) Be sure to go through the using Modelsim portion of the handbook(although you may already have).