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Altera_Forum
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17 years ago

problem with verilog simulation in modelsim altera

the following error is being shown when i'm performing timing simulation on my verilog design: Instantiation of 'dffeas' failed. The design unit was not found. all my vhdl designs have worked...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

hi all,

i tried a different approach this time around. i created a modelsim project and included the required libraries in the project itself. but now, modelsim is showing an error say that compiled sdf file is not found. i included all the necessary sdo files generated by the time quest time analyser tool in the SDF tab. can anyone help me solving this problem?

thanks,

Sumanth.