Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

problem with verilog simulation in modelsim altera

the following error is being shown when i'm performing timing simulation on my verilog design: Instantiation of 'dffeas' failed. The design unit was not found. all my vhdl designs have worked...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I see, that you already spend some effort on the issue. Unfortunately, I'm not so familiar to the hierarchy of Verilog ModelSim libraries. I'm using ModelSim mostly with VHDL and also needed several attempts when occasionally simulating pure Verilog designs.

However, I think, Altera primitives can't be found in a work library. There should be additional libraries imported by vsim that contains them.

May be, another forum member is more experienced to Verilog simulation. Good luck!