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Altera_Forum
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17 years ago

problem with verilog simulation in modelsim altera

the following error is being shown when i'm performing timing simulation on my verilog design: Instantiation of 'dffeas' failed. The design unit was not found. all my vhdl designs have worked...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

hi fvm,

i recompiled the altera_ver library in modelsim_ae. the "dffeas" component was present. but the vsim command is somehow searching "dffeas" in a library called gate_work instead of work. can u suggest means to work around this problem?

thanks,

sumanth