Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorproblem with verilog simulation in modelsim altera
the following error is being shown when i'm performing timing simulation on my verilog design: Instantiation of 'dffeas' failed. The design unit was not found. all my vhdl designs have worked...
Altera_ForumHonored Contributor
Honored ContributorIn Verilog simulation, you have to care to import the necessary libraries. In VHDL simulation, this is mostly done from library USE statements automaticly. However dffeas seems to be an Altera primitive that should be present in the default Verilog libraries.
