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Altera_Forum's avatar
Altera_Forum
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17 years ago

problem with verilog simulation in modelsim altera

the following error is being shown when i'm performing timing simulation on my verilog design: Instantiation of 'dffeas' failed. The design unit was not found. all my vhdl designs have worked...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

In Verilog simulation, you have to care to import the necessary libraries. In VHDL simulation, this is mostly done from library USE statements automaticly. However dffeas seems to be an Altera primitive that should be present in the default Verilog libraries.