Problem with Stratix IV m9k mem read

The memory blocks in recent Altera FPGAs are synchronous only and don't support asynchronous access. When you do an asynchronous assignment, the synthesizer guesses which clock to use depending on how you synchronize the address and/or the data. In your case it may have selected the wrong clock.

To be sure that the synthesizer instantiates what you want, you should stick to the recommended HDL coding style in this document: http://www.altera.com/literature/hb/qts/qts_qii51007.pdf

Have a look at the "Simple Dual-Port, Dual-Clock Synchronous RAM" example on pages 6-22 and 6-23.