Problem with port mapping in Quartus

I have figured out the problem. In this design both the CLK and the CE have 16 fan outs. If I change atleast one such that its fan-out becomes 8 or less then the problem is sorted. However, since I am going to use this block as a part of a larger design I cannot have more than one clock. I, therefor, planned to split the fan-out of CE. I designed a CE block which produces two high outputs if the input which is the original clock enable is high. Now I used the Input and the output of these blocks as CEs. The code is given here

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Memoryblock is

Port ( Input : in STD_LOGIC_VECTOR (15 downto 0);

Output : out STD_LOGIC_VECTOR (15 downto 0);

CLK : in STD_LOGIC;

-- CE1 : inout std_logic;

-- CE2 : inout std_logic;

CLR : in STD_LOGIC;

CE : in STD_LOGIC);

end Memoryblock;

architecture Behavioral of Memoryblock is

signal CE1 : std_logic;

signal CE2 : std_logic;

component MEMBLOCK is

Port ( Input : in STD_LOGIC;

CLK : in STD_LOGIC;

CLR : in STD_LOGIC;

CE : in std_logic;

Output : out STD_LOGIC);

end component;

component ClockEnable is

port(CE : in std_logic;

CE1 : out std_logic;

CE2 : out std_logic);

end Component;

begin

C : ClockEnable

port map(CE, CE1, CE2);

A0 : MEMBLOCK

port map( Input(0), CLK, CLR, CE, Output(0));

A1 : MEMBLOCK

port map( Input(1), CLK, CLR, CE, Output(1));

A2 : MEMBLOCK

port map( Input(2), CLK, CLR, CE, Output(2));

A3 : MEMBLOCK

port map( Input(3), CLK, CLR, CE, Output(3));

A4 : MEMBLOCK

port map( Input(4), CLK, CLR, CE, Output(4));

A5 : MEMBLOCK

port map( Input(5), CLK, CLR, CE1, Output(5));

A6 : MEMBLOCK

port map( Input(6), CLK, CLR, CE1, Output(6));

A7 : MEMBLOCK

port map( Input(7), CLK, CLR, CE1, Output(7));

A8 : MEMBLOCK

port map( Input(8), CLK, CLR, CE1, Output(8));

A9 : MEMBLOCK

port map( Input(9), CLK, CLR, CE1, Output(9));

A10 : MEMBLOCK

port map( Input(10), CLK, CLR, CE1, Output(10));

A11 : MEMBLOCK

port map( Input(11), CLK, CLR, CE2, Output(11));

A12 : MEMBLOCK

port map( Input(12), CLK, CLR, CE2, Output(12));

A13 : MEMBLOCK

port map( Input(13), CLK, CLR, CE2, Output(13));

A14 : MEMBLOCK

port map( Input(14), CLK, CLR, CE2, Output(14));

A15 : MEMBLOCK

port map( Input(15), CLK, CLR, CE2, Output(15));

end Behavioral;

The problem is if I use the CE1 and CE2 as signals then the CE has again a fan-out of 16. I have to use them as inout ports which is a little difficult as the block is part of a larger design. How can I sort my problem out? Please help!!!