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Altera_Forum's avatar
Altera_Forum
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15 years ago

Problem with port mapping in Quartus

Hello, I am trying to model a two dimensional array of registers using port mapping in quartus. I have first designed a five stage shift register for which I am getting the desired result i.e., th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

The only possible issue with the code, is the fact you have the CE on the same line as a the clock. Usually it is common to separate a clock enable from the clock, ie: 


if rising_edge(clk) then
  if CE = '1' then
    .....
  end if;
end if;

But I doubt this is causing the issue. There is otherwise nothing wrong with the code. Im guessing the problem is elsewhere. Wherre are you seeing the problem? RTL simulation? gate level simulation? on the chip?