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Altera_Forum
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13 years ago

Problem with LVDS via HSMC on Cyclone III Development Kit

Hello everyone,

I am using a TI ADC Daughter Card with a Cyclone III Development Kit. I connected the ADC Card via HSMC. There are 2 channels with 6 LVDS DDR input pins.

I watched these Signal ins Signal Tap and some of the data signal showed the expected values while some where allways on high level and some allways on low level. I checked the signal on the ADC Board (without the FPGA board beeing connected to i) with an oszilloscpe and they look just fine. When I connect the ADC board, some of the signals are distorted.

The attached picture shows the signal tap traces and the signals that are on high level here are allways on high level. The screenshot was taken when the ADC board was not connected!!!! This is what confuses me!! Can anybody help me?

The second picture shows the traces with the ADC connected in a testmode where it toggles every bit with each clock.

Thank you very much in advance!!!

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    I am using a TI ADC Daughter Card with a Cyclone III Development Kit. I connected the ADC Card via HSMC. There are 2 channels with 6 LVDS DDR input pins.

    --- Quote End ---

    Which Cyclone III kit specifically?

    I just looked at the schematic for one of the Cyclone III kits, c3_f780_host.pdf, and on page 15 there are HSMC 100-ohm terminations for each of the LVDS receiver signals.

    Have you installed those terminations?

    Cheers,

    Dave