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Altera_Forum's avatar
Altera_Forum
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8 years ago

Problem with FSM on Hardware testing

Hello All, I have designed Manchester Decoder in System Verilog using 2 always block method. But in testing on hardware, I am analyzing outputs in SignalTap and it is found that after reset one...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

yes, divyaganti it is stuck in reset.

But I got a solution for this issue.

As I have taken input from a gateway, I have used that signal directly in FSM, but now I have taken a flop of that signal and then used that flop in FSM and It starts working.

Again thank you to both of you for your warm replies.