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Honored Contributor
Honored ContributorProblem with FSM on Hardware testing
Hello All, I have designed Manchester Decoder in System Verilog using 2 always block method. But in testing on hardware, I am analyzing outputs in SignalTap and it is found that after reset one...
Altera_ForumHonored Contributor
Honored ContributorI am a little confused. How many states do you have in total?
--- Quote Start --- If my FSM is stuck in any one state then I can solve out this by modifying some conditions in the if..else loop but here in my case, FSM does not stay in any case of five cases of FSM --- Quote End --- Is it stuck in reset? Do you mean that it jumps through the initial states, but it does not transition to any of the states that you want it to transition to? If you are using signal tap to debug, you can add the State machine nodes directly. Right click -> Add state machine nodes -> Select the statemachine. This can give you more information. If it works properly in simulation, it could be that some of your input triggers that you provide from the testbench, might have been trimmed in synthesis. Like Anand Raj said, it would be more helpful if you provide the code.
