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Altera_Forum's avatar
Altera_Forum
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8 years ago

Problem with FSM on Hardware testing

Hello All, I have designed Manchester Decoder in System Verilog using 2 always block method. But in testing on hardware, I am analyzing outputs in SignalTap and it is found that after reset one...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

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1.Have you simulated the code?

(This message was posted on behalf of Intel Corporation)

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thank you sir for your reply.

Yes I have simulated the code in Quartus 16.1

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2.try to use altera quartus template.

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You mean to say that I should use the same method as given in Altera Quartus template. ?