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Altera_Forum
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8 years ago

Problem with FSM on Hardware testing

Hello All, I have designed Manchester Decoder in System Verilog using 2 always block method. But in testing on hardware, I am analyzing outputs in SignalTap and it is found that after reset one...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi,

Double check that all possible transitions out of the state after the first frame is decoded are taken care of. For example, if you have a bunch of If else conditions, or a case statement, make sure you either have a default next state defined, or ensure that each subsection has a next state defined.

From what you have written about your problem, it looks like it is stuck in the same state . This could be that your default action is to remain in that state till you receive an input to transition to the next state, and it never receives it. Check if the conditions that you are waiting for is a valid one.