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Altera_Forum
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8 years ago

Problem with FSM on Hardware testing

Hello All, I have designed Manchester Decoder in System Verilog using 2 always block method. But in testing on hardware, I am analyzing outputs in SignalTap and it is found that after reset one...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi,

Output may be latched due output ports handing can you check once.

1.Have you simulated the code?

2.Can you provide code?

Or

try to use altera quartus template.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)