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Altera_Forum
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18 years ago

Problem with EPM1270T144I5N programming

I have a problem with EPM1270T144I5N programming. Nearly half of the same batch (45 pieces) of this device failed to complete ISP. I'm a totally green thumb in this field and don't know how t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hi,

Apparently both of the device lots that are failing are based on die revision G, which may be suffering from issue "Failed power-up into user mode for slow VCCINT rise times or VCCINT rise profiles with dips or noise near the power-on reset (POR) trip voltage." Please refer to http://www.altera.com/literature/ds/es_max_ii.pdf for more details.

You could give it a try with new chips containing die revision code I or later to make sure that this does not occur. I don't know whether it would be possible for you to experiment with this, but let me know if you do get a chance to experiment.

Hope this helps.

Cheers,

BD