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Altera_Forum
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10 years ago

Problem with dynamic PLL reconfiguration

I am working on a project which involves dynamically configuring PLL to different frequencies. I have written a VHDL code for my requirement, however I am facing some circumstances in simulation w...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hi Nic,

In the snapshot above rst_usr is the signal that is input as reset to PLL.

For better clarity I have attached another snapshot with pll rst, lock and pll output clock coloured in yellow.

Note that lock is not getting low even after reset is asserted.